회사 소개
㈜스타칩스는 2024년 9월 ASIC 전문 업체로 법인 설립되었습니다.
㈜스타칩스는 Fabless 와 Foundry를 위한 ASIC 전문 기술 업체입니다.
㈜스타칩스는 180nm에서부터 7nm Deep sub micron 까지의 풍부한 경험을 가진 엔지니어들로 구성되어 있으며 ASIC Design Service 의 선두 주자로 나아갈 것 입니다.
㈜스타칩스는 다수의 국내 반도체 회사와의 설계 협력 관계를 구축하여 Fabless IC 고객사들에게 Non-Stop & One time Success 를 할 수 있는 최고의 반도체 기술 회사가 되고자 최선을 다하겠습니다.
㈜스타칩스는 반도체 설계 엔지니어와의 동반자로서 또한 반도체 개발 양산 지원의 Leader로서 반도체 업체들의 수익과 성장에 밑바탕이 되어드리겠습니다.
ASIC Design
Design Entry
Using a hardware description language (HDL) or schematic entry.
Logic Synthesis
Produce a gate-level netlist. Logic cells and their nets connection.
DFT Implementation
Insert Test Logic for logic cells, memory, IP.
Pre-layout Simulation
Check to see if gate-level netlist design functions correctly.
Floor Planning
Arrange the blocks of the netlist on the chip.
Placement
Decide the locations of cells in a block.
CTS
Inserting buffers/inverters along the clocks path of the ASIC design to balance the clock delay.
Routing
Make the connections between cells and blocks.
Physical Verification
Ensuring a design's layout works as intended. Steps include design rule checking (DRC) and layout-versus-schematic (LVS) checks.
IR-DROP
Check to static and dynamic voltage drop.
Post-layout Simulation
Check to see the design still works with the added loads of the interconnect.
GDS Out
Delivers GDS (Graphic Database System) to the process.
Our Services
Physical Implementation
- Synthesis for Area & Timing Optimized
- SDC Clean up for Constraints error fix
- Static Timing Analysis for setup & hold & mttv & noise timing violation fix
- Simulation for function check
- Test Vector Generation
Physical Design
- FloorPlan for Area Reduced & Timing Optimized about Macro Location
- Place for Standard cells
- Clock Tree Synthesis
- Route for Physical cells connection
- IR-DROP for Static & Dynamic Power check
- RDL for BUMP Design
- Physical Verification for DRC & LVS & ESD & ANT
Design For Test
- Clock Generation for DFT
- IO MUX for DFT
- SCAN Insert & Verify for custom fault coverage target meet
- MBIST Insert & Verify for Memory Test
- IP Direct Access Test for IP Integration Design
Our Clients
Trusted by leading semiconductor companies
TSMC
Samsung
GlobalFoundries
Intel
And many more industry leaders...
Contact Us
